Xilinx HDMI TX Subsystem

The Xilinx HDMI TX Subsystem contains several subcores to implement
a HDMI Transmitter. xilinx_drm_hdmi.c implements a DRM/KMS driver
encoder/connector interface in the output pipeline.

There are 2 optional HDCP cores that can be included in the IP configuration.
Below provided sample device tree depicts the configuration when both cores are
included. If an optional core is included then corresponding entries for the
core parameters (interrupts, key-management block address) must be included in
the device tree

Note: If HDCP cores are included in the design, the user must provide valid
	  HDCP keys for the encryption to work.

Note: This version of the driver interfaces with the new Xilinx DRM component
	  framework and is not backward compatible with the earlier encoder-slave
	  interface. As such compatibility string has been reved up to indicate the
	  new interface.

Refer to xlnx,vphy.txt for the phy specifics.

Required properties:
 - compatible: Should be "xlnx,v-hdmi-tx-ss-3.1".
 - reg: Base address and size of the IP core and hdcp1x key management block
 - reg-names: Identification string for included register blocks
		"hdmi-txss": Identification string for hdmitx subsystem. Always present
		"hdcp1x-keymngmt": Identification string for Key management block for
			hdcp1x. [Optional]

 - interrupts-parent: phandle for interrupt controller.
 - interrupts: Interrupt numbers for mandatory and optional blocks
 - interrupt-names: Identification string that binds irq number to block
		generating the interrupt
		"irq": interrupt for tx subcore [always present]
		"hdcp14_irq": interrupt for hdcp1.4 core [optional - present if hdcp1x
		is included]
		"hdcp14_timer_irq": interrupt for hdcp1.4 timer [optional - present if
		hdcp1x is included]
		"hdcp22_irq": interrupt for hdcp22 core [optional - present if hdcp22
		is included]
		"hdcp22_timer_irq": interrupt for hdcp2.2 timer [optional - present if
		hdcp22 is included]

 - clocks: phandle of all the clocks required by IP are listed here.
 - clock-names: names of all the clocks required by IP are listed here.
          NOTE: Auto generated DT is providing all the clock names and handles
          reuired by the IP.
          NOTE: Below are the identification string that are always required.
              "s_axi_cpu_aclk", is always required for the axi-lite clock
              "s_axis_video_aclk" is always required for video stream clock
              "txref-clk" is always required for tmds clock
              "retimer-clk" is required only when retimer is being used
          NOTE: "txref-clk" and "retimer-clk" needs to be explicitly added in
          the list of clock-names and its phandle in clocks as its derived by
          external clock.

 - phys: phandle for phy lanes registered for hdmi protocol. HDMI always
         require 3 lanes
 - phy-names: The identification string, "hdmi-phy0" and so on

 - xlnx,input-pixels-per-clock: IP configuration for samples/clk (2, 4)
         Note: Only 2 is supported at this time
 - xlnx,max-bits-per-component: The data width per video component (8,10,12,16)
         Note: Only 8 & 10 is supported at this time
 - xlnx,include-hdcp-1-4: Boolean parameter that denotes if hdcp14 is included.
		If present indicates inclusion of the optional core
 - xlnx,include-hdcp-2-2: Boolean parameter that denotes if hdcp22 is included.
		If present indicates inclusion of the optional core
 - xlnx,hdcp-authenticate: Flag to enable/disable hdcp authentication.
		Applicable when either hdcp14 or hdcp22 is included in the design
 - xlnx,hdcp-encrypt: Flag to enable/disable stream encryption
 		Applicable when either hdcp14 or hdcp22 is included in the design
 - xlnx,audio-enabled: Boolean parameter to convey that design has audio
                functionality.
		If present, indicates optional audio core needed for audio
		usecase is included.
 - xlnx,aes_parser: Alias to audio channel status extractor block.
		Needed only if "xlnx,audio-enabled" is included.
 - xlnx,snd-pcm: Reference to audio formatter block. Add this if, audio formatter
                is going to be used for HDMI audio.
		Needed only if "xlnx,audio-enabled" is included.
 - xlnx,xlnx-hdmi-acr-ctrl: Alias to audio clock recovery block.
		Needed only if "xlnx,audio-enabled" is included.
 - xlnx,vid-interface: Indicates the video interface mode (0, 1, 2)
		0: AXI-stream
		1: Native video
		2: Native video (vectored DE)

Sub-Node Properties:
	The device tree will need to include a sub-node for the encoder endpoint
	interface. This port will bind the hdmi encoder with the crtc being used

	Required Properties:
	- ports: Connects to the crtc node through the device graph binding.
	The port should contain a 'remote-endpoint' sub-node that points to the
	endpoint in the port of the crtc/dma-engine device node.

The "retimer-clk" is optional but recommended. If specified, the corresponding
driver should offer a CCF clock that supports .set_rate(). Through this,
the device can retime/redrive the HDMI TX signal on the connector
depending on the TX clock line rate. Tested with dp159.c driver.

==Example==
If hdcp1.4 is included in the design then key management block node should be
added to the device tree

	hdcp_keymngmt_blk_0: hdcp_keymngmt_blk_top@90000000 {
		clock-names = "s_axi_aclk", "m_axis_aclk";
		clocks = <&zynqmp_clk 71>, <&misc_clk_0>;
		compatible = "xlnx,hdcp-keymngmt-blk-top-1.0";
		reg = <0x0 0x90000000 0x0 0x10000>;
	};

	hdmi_acr_ctrl_0: hdmi_acr_ctrl@a0059000 {
		/* This is a place holder node for a custom IP, user may need to update the entries */
		compatible = "xlnx,hdmi-acr-ctrl-1.0";
		reg = <0x0 0xa0059000 0x0 0x1000>;
	};

	v_hdmi_tx_ss: v_hdmi_tx_ss@80080000 {
		compatible = "xlnx,v-hdmi-tx-ss-3.1";
		reg = <0x0 0xa0080000 0x0 0x80000>, <0x0 0xa0280000 0x0 0x10000>;
		reg-names = "hdmi-txss", "hdcp1x-keymngmt";
		interrupt-parent = <&gic>;
		interrupts = <0 91 4 0 106 4 0 107 4 0 110 4 0 111 4>;
		interrupt-names = "irq", "hdcp14_irq", "hdcp14_timer_irq", "hdcp22_irq", "hdcp22_timer_irq";

		clock-names = "s_axi_cpu_aclk", "link_clk", "s_axis_audio_aclk", "video_clk", "s_axis_video_aclk", "txref-clk", "retimer-clk";
		clocks = <&zynqmp_clk 71>, <&misc_clk_1>, <&zynqmp_clk 71>, <&misc_clk_2>, <&zynqmp_clk 72>, <&si5324 0>, <&dp159>;
		phy-names = "hdmi-phy0", "hdmi-phy1", "hdmi-phy2";
		phys = <&vphy_lane0 0 1 1 1>, <&vphy_lane1 0 1 1 1>, <&vphy_lane2 0 1 1 1>;

		xlnx,input-pixels-per-clock = <0x2>;
		xlnx,max-bits-per-component = <0xa>;
		xlnx,include-hdcp-1-4;
		xlnx,include-hdcp-2-2;
		/* settings for HDCP */
		xlnx,hdcp-authenticate = <0x1>;
		xlnx,hdcp-encrypt = <0x1>;
		xlnx,audio-enabled;
		xlnx,xlnx-hdmi-acr-ctrl = <&hdmi_acr_ctrl_0>;
		xlnx,snd-pcm = <&audio_ss_0_audio_formatter_0>;
		xlnx,vid-interface = <0x1>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			encoder_hdmi_port: port@0 {
				reg = <0>;
				hdmi_encoder: endpoint {
					remote-endpoint = <&dmaengine_crtc>;
				};
			};
		};
	};

	v_drm_dmaengine_drv: drm-dmaengine-drv {
		compatible = "xlnx,pl-disp";
		dmas = <&hdmi_output_v_frmbuf_rd_0 0>;
		dma-names = "dma0";
		xlnx,vformat = "BG24";
		#address-cells = <1>;
		#size-cells = <0>;
		dmaengine_port: port@0 {
			reg = <0>;
			dmaengine_crtc: endpoint {
				remote-endpoint = <&hdmi_encoder>;
			};
		};
	};

	Documentation of "audio_ss_0_audio_formatter_0" node is located
	at Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt
